A Compact and High-Performance Hardware Architecture for CRYSTALS-Dilithium

نویسندگان

چکیده

The lattice-based CRYSTALS-Dilithium scheme is one of the three thirdround digital signature finalists in National Institute Standards and Technology Post-Quantum Cryptography Standardization Process. Due to complex calculations highly individualized functions Dilithium, its hardware implementations face problems large area requirements low efficiency. This paper proposes several optimization methods achieve a compact high-performance architecture for round 3 Dilithium. Specifically, segmented pipelined processing method proposed reduce both storage time. Moreover, optimized modules are designed improve efficiency architecture, including number theoretic transform module, SampleInBall Decompose modular reduction modules. Compared with state-of-the-art designs Dilithium on similar platforms, our implementation requires 1.4×/1.4×/3.0×/4.5× fewer LUTs/FFs/BRAMs/DSPs, respectively, 4.4×/1.7×/1.4× less time key generation, verification, NIST security level 5.

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ژورنال

عنوان ژورنال: IACR transactions on cryptographic hardware and embedded systems

سال: 2021

ISSN: ['2569-2925']

DOI: https://doi.org/10.46586/tches.v2022.i1.270-295